The trend in the semiconductor industry today is the production of ever increasingly more capable semiconductor components, while decreasing component size and total semiconductor package height. QFN/LGA configurations are popular methods to realize increased semiconductor device density. With the need to achieve ever smaller package sizes and thinner package heights being an ongoing driver, new methodologies are sought.
FIG. 1A is a cross-sectional view of a Quad Flat No Leads configuration semiconductor package. As is well known in the art, QFN configurations are used to physically and electrically connect semiconductor devices making up integrated circuits to printed circuit boards. As illustrated in FIG. 1A, a semiconductor chip 102 is placed onto a substrate 104. In an exemplary embodiment, an adhesive 106 is used to bind the semiconductor chip 102 to the substrate 104. Wire loops 108 electrically connect the semiconductor chip 102 to the substrate 104. However, as further illustrated in FIG. 1A, the semiconductor chip die 102 thickness, the above mentioned wire loops 108, encapsulating material 110 thickness (as determined by the encapsulating mold thickness), and substrate material 104 thickness, all contribute to the overall package thickness and will result in overall package thicknesses in excess of 300 microns.
FIG. 1B is a cross-sectional view of a semiconductor configuration as disclosed by Asada (U.S. Pat. No. 6,239,496), hereinafter “Asada.” As illustrated in FIG. 1B, the substrate 152 is an insulating polymide film 50-75 microns thick with 18 micron thick copper traces 154 laid onto it, with the copper traces laid as a thin film laminated to the substrate 152 which is later patterned. A semiconductor chip die 156 is electrically connected to the substrate 152 through gold bumps 158. The semiconductor chip 156 is allowed to flex using an anisotropically conductive adhesive as the connecting resin 160 that attaches the semiconductor chip 156 to the substrate 152. Lastly, the semiconductor chip die 156 is 50 microns thick. Therefore, as Asada discloses, and as illustrated in FIG. 1B, the semiconductor chip 156 thickness, the copper lead 154 thickness and the substrate 152 thickness still result in an overall semiconductor package thickness of about 200 microns.